Tobias Breiten, Markus Kantner, Thomas Koprucki
01.04.2023 − 31.03.2026
Spin qubits in gate-defined semiconductor quantum dots (QDs) are one of the major candidates for the realization of fault-tolerant universal quantum computers. Ongoing advances in the growth of SiGe heterostructures with isotopically purified 28Si quantum wells that have zero nuclear spin have enabled exceptionally long coherence times. Moreover, the compatibility with industry standard fabrication technology opens up excellent prospects for scaling up Si/SiGe-based quantum processors to very large numbers of qubits. Recently, small-scale devices have been demonstrated, which execute one- and two-qubit logic gates as well as initialization and read-out operations with high fidelity using all-electrical control.
The wiring and interconnection of large arrays of tunnel-coupled QDs, however, is a challenging problem as numerous control signals must be routed from external sources to every QD. While control lines can be stacked in multiple layers, there are clear limitations in view of geometric constraints. A possible solution to this fan-out problem is partitioning of the qubit register into smaller QD arrays interconnected by coherent quantum links, which allow to shuttle electrons in a conveyor belt mode along a one-dimensional channel.
This project is devoted to modeling, simulation and optimal control of quantum bus devices for scalable semiconductor-based quantum processors. The key objectives of the project are: